View NCP1397BDR2G_4005511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2011 january, 2011 ? rev. 3 1 publication order number: ncp1397/d ncp1397a, ncp1397b high performance resonant mode controller with integrated high-voltage drivers the ncp1397 is a high performance controller that can be utilized in half bridge resonant topologies such as series resonant, parallel resonant and llc resonant converters. it integrates 600 v gate drivers, simplifying layout and reducing external component count. with its unique architecture, including a 500 khz voltage controlled oscillator whose control mode permits flexibility when an oring function is required, the ncp1397 delivers everything needed to build a reliable and rugged resonant mode power supply. the ncp1397 provides a suite of protection features with configurable settings to optimize any application. these include: auto ? recovery or fault latch ? off, brown ? out, open optocoupler, soft ? start and short ? circuit protection. deadtime is also adjustable to overcome shoot through current. features ? high ? frequency operation from 50 khz up to 500 khz ? 600 v high ? voltage floating driver ? adjustable minimum switching frequency with 3% accuracy ? adjustable deadtime from 100 ns to 2 s. ? startup sequence via an externally adjustable soft ? start ? brown ? out protection for a simpler pfc association ? latched input for severe fault conditions, e.g. over temperature or ovp ? timer ? based input with auto ? recovery operation for delayed event reaction ? latched overcurrent protection ? disable input for immediate event reaction or simple on/off control ? v cc operation up to 20 v ? low startup current of 300 a ? 1 a / 0.5 a peak current sink / source drive capability ? common collector optocoupler connection for easier oring ? optional common emitter optocoupler connection ? internal temperature shutdown ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? flat panel display power converters ? high power ac ? dc adapters for notebooks ? computing power supplies ? industrial and medical power sources ? offline battery chargers pin connections http://onsemi.com marking diagrams x = a or b a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package so ? 16, less pin 13 d suffix case 751am 1 16 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) bo css(dis) fmax ctimer rt fb dt skip/disable vboot mupper v cc mlower fault hb gnd see detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. ordering information 1 16 ncp1397xg awlyww
ncp1397a, ncp1397b http://onsemi.com 2 figure 1. typical application example r18 pin function description pin # pin name function pin description 1 css(dis) soft ? start discharge soft ? start capacitor discharge pin. connect to the soft ? start capacitor to reset it before startup or during overload conditions. 2 fmax maximum frequency clamp a resistor sets the maximum frequency excursion 3 ctimer timer duration sets the timer duration in presence of a fault 4 rt minimum frequency clamp connecting a resistor to this pin, sets the minimum oscillator frequency reached for v fb = 1 v. 5 bo brown ? out detects low input voltage conditions. when brought above v latch (4 v typically), it fully latches off the controller. 6 fb feedback injecting current into this pin increases the oscillation frequency up to fmax. 7 dt deadtime a simple resistor adjusts the dead ? time width 8 skip/disable skip or disable input upon release, a clean startup sequence occurs if v fb < 0.3 v. during the skip mode, when fb doesn?t drop below 0.3 v, the ic restarts without soft ? start sequence. 9 fault fault detection input when asserted, the external timer starts to countdown and shuts down the controller at the end of its time duration. simultaneously the soft ? start discharge switch is activated so the converter operating frequency goes up to protect application power stage. this input features also second fault comparator with higher threshold (1.5 v typically) that: a) speeds up the timer capacitor charging current 8 times ? ncp1397a b) latches off the ic permanently ? ncp1397b in both versions the second fault comparator helps to protect application in case of short circuit on the output or transformer secondary winding. 10 gnd analog ground ? 11 mlower low side output drives the lower side mosfet 12 v cc supplies the controller the controller accepts up to 20 v 13 nc not connected increases the creepage distance 14 hb half ? bridge connection connects to the half ? bridge output 15 mupper high side output drives the higher side mosfet 16 vboot bootstrap pin the floating v cc supply for the upper stage
ncp1397a, ncp1397b http://onsemi.com 3 figure 2. internal circuit architecture (ncp1397a) vref rt vdd c idt ? ? + + dt adj. i = imax for vfb = 5.3 v i = 0 for vfb < vfb(min) imin vfb vfb(o ) vref vdd imax vfb = 5 fmax vdd itimer1 ? ? + timer + vref pon reset vtimer off reset ss(dis) fb rfb ? ? + + vfb(fault) ? ? + g = 1 > 0 only v=v (fb) ? ? vfb(min) idt vref vdd + vfb(min) dt deadtime adjustment vdd ? ? + bo + vbo ? ? + + vlatch clk d s q q r s q q r pon reset 50% dc temperature shutdown vcc management pon reset fault timeout fault vref bo reset ff + ? ? + vref skip/disable skip/ disable v cc timeout fault fault mlower gnd ibo 20 ns noise filter + ? ? fault + vref(fault) nc v boot mupper hb uvlo fast fault + ? ? + vref(ocp) vdd itimer2 level shifter 1 m s noise filter 20 m s noise filter 20 m s noise filter fault pon reset enable (if vfb<0.3v)
ncp1397a, ncp1397b http://onsemi.com 4 figure 3. internal circuit architecture (ncp1397b) vref rt vdd c idt ? ? + + dt adj. i = imax for vfb = 5.3 v i = 0 for vfb < vfb_min vref imin vfb vfb(o ) vref vdd imax vfb = 5 fmax vdd itimer1 if fault itimer else 0 ? ? + timer + vref ss(dis) fb rfb ? ? + + vfb(fault) ? ? + g = 1 > 0 only v=v (fb) ? ? vfb(min) idt vref vdd + vfb(min) dt deadtime adjustment vdd ? ? + bo + vbo ? ? + + vlatch clk d s q q r s q q r pon reset 50% dc temperature shutdown vcc management pon reset fault timeout fault vref bo reset ff + ? ? + vref skip skip/ disable v cc timeout fault fault mlower gnd ibo 20 ns noise filter + ? ? fault + vref(fault) nc v boot mupper hb uvlo level shifter fast fault + ? ? + vref(ocp) 1 m s noise filter 20 m s noise filter 20 m s noise filter pon reset vtimer off reset fault pon reset enable (if vfb<0.3v)
ncp1397a, ncp1397b http://onsemi.com 5 maximum ratings rating symbol value unit high voltage bridge pin, pin 14 v bridge ? 1 to 600 v floating supply voltage, ground referenced v boot ? v bridge 0 to 20 v high side output voltage v drv(hi) v bridge ? 0.3 to v boot +0.3 v low side output voltage v drv(lo) ? 0.3 to v cc +0.3 v allowable output slew rate dv bridge /dt 50 v/ns power supply voltage, pin 12 v cc 20 v maximum voltage, all pins (except pin 11 and 10) ? ? 0.3 to 10 v thermal resistance junction ? to ? air, pdip version r ja 100 c/w thermal resistance junction ? to ? air, soic version r ja 130 c/w storage temperature range ? ? 60 to +150 c esd capability, human body model (hbm) (all pins except hv pins) ? 2 kv esd capability, machine model (mm) ? 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22 ? a114e machine model 200 v per jedec standard jesd22 ? a115 ? a 2. this device meets latchup tests defined by jedec standard jesd78.
ncp1397a, ncp1397b http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section v cc(on) turn ? on threshold level, v cc going up 12 9.7 10.5 11.3 v v cc(min) minimum operating voltage after turn ? on 12 8.7 9.5 10.3 v v boot(on) startup voltage on the floating section 16 ? 14 8 9 10 v v boot(min) cutoff voltage on the floating section 16 ? 14 7.4 8.4 9.4 v i startup startup current, v cc < v cc(on) 12 ? ? 300 a v cc(reset) v cc level at which the internal logic gets reset 12 ? 6.6 ? v i cc1 internal ic consumption, no output load on pin 15/14 ? 11/10, f sw = 300 khz 12 ? 4 ? ma i cc2 internal ic consumption, 1 nf output load on pin 15/14 ? 11/10, f sw = 300 khz 12 ? 11 ? ma i cc3 consumption in fault or disable mode (all drivers disabled, rt = 34 k , r dt = 10 k ) 12 ? 1.5 ? ma voltage control oscillator (vco) f sw(min) minimum switching frequency, rt = 34 k on pin 4, v pin6 = 0.8 v, dt = 300 ns 4 58.2 60 61.8 khz f sw(max) maximum switching frequency, r f(max) = 1.9 k on pin 2, v pin6 > 5.3 v, rt = 34 k , dt = 300 ns 2 440 500 560 khz fb sw feedback pin swing above which f = 0 6 ? 5.3 ? v dc operating duty ? cycle symmetry 11 ? 15 48 50 52 % t del1 delay before driver restart from fault or disable mode ? ? 700 ? ns t del2 delay before driver restart after v cc(on) event (note 4) ? ? 11 ? s v ref(rt) reference voltage for rt pin 4 2.18 2.3 2.42 v feedback section r fb internal pulldown resistor 6 ? 20 ? k v fb(min) voltage on pin 6 below which the fb level has no vco action 6 ? 1.1 ? v v fb(off) voltage on pin 6 below which the controller considers the fb fault 6 240 280 320 mv v fboff(hyste) feedback fault comparator hysteresis 6 ? 45 ? mv drive output t r output voltage risetime @ c l = 1 nf, 10 ? 90% of output signal 15 ? 14/11 ? 10 ? 40 ? ns t f output voltage falltime @ c l = 1 nf, 10 ? 90% of output signal 15 ? 14/11 ? 10 ? 20 ? ns r oh source resistance 15 ? 14/11 ? 10 ? 13 ? r ol sink resistance 15 ? 14/11 ? 10 ? 5.5 ? t dead deadtime with r dt = 10 k from pin 7 to gnd 7 250 290 340 ns t dead(max) maximum deadtime with r dt = 82 k from pin 7 to gnd 7 ? 2 ? s t dead(min) minimum deadtime, r dt = 3 k from pin 7 to gnd 7 ? 100 ? ns i hv(leak) leakage current on high voltage pins to gnd 14, 15,16 ? ? 5 a timers i timer1 timer capacitor charge current during feedback fault or when v ref(fault) < v pin9 < v ref(ocp) 3 150 175 190 a 3. the ic does not activate soft ? start (unless the feedback pin voltage is below 0.3 v) when the skip/disable input is released, this is for skip cycle implementation. 4. guaranteed by design.
ncp1397a, ncp1397b http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating timers i timer2 timer capacitor charge current when v pin9 > v ref(ocp) (i charge1 + i charge2 ) ? a version only 3 1.1 1.3 1.5 ma t timer timer duration with a 1 f capacitor and a 1 m resistor, i timer1 current applied 3 ? 24 ? ms t timerr timer recurrence in permanent fault, same values as above 3 ? 1.4 ? s v timer(on) voltage at which pin 3 stops output pulses 3 3.8 4 4.2 v v timer(off) voltage at which pin 3 restarts output pulses 3 0.95 1 1.05 v r ss(dis) soft ? start discharge switch channel resistance 1 ? 100 ? protection v ref(skip) reference voltage for skip/disable input (note 4) 8 630 660 690 mv hyste (skip) hysteresis for skip/disable (note 4) 8 ? 45 ? mv v ref(fault) reference voltage for fault comparator 9 0.99 1.04 1.09 v hyste (fault) hysteresis for fault comparator input 9 ? 60 ? mv v ref(ocp) reference voltage for ocp comparator 9 1.47 1.55 1.63 v hyste (ocp) hysteresis for ocp comparator input 9 ? 90 ? mv t p(disable) propagation delay from disable input to the drive shutdown 8 ? 60 100 ns ibo (bias) brown ? out input bias current 5 ? 0.02 ? a vbo brown ? out level 5 0.99 1.04 1.09 v ibo hysteresis current, v pin5 > vbo 5 25 28 31 a vl atch latching voltage 5 3.7 4 4.3 v t sd temperature shutdown ? 140 ? ? c t sd(hyste) hysteresis ? ? 30 ? c 3. the ic does not activate soft ? start (unless the feedback pin voltage is below 0.3 v) when the skip/disable input is released, this is for skip cycle implementation. 4. guaranteed by design.
ncp1397a, ncp1397b http://onsemi.com 8 typical characteristics 10.35 10.40 10.45 10.50 10.55 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 4. v cc(on) threshold v cc(on) (v) temperature ( c) figure 5. v cc(min) threshold 9.38 9.40 9.42 9.44 9.46 9.48 9.50 9.52 ? 40 ? 25 ? 105 203550658095110125 temperature ( c) v cc(min) (v) f sw(min) (khz) temperature ( c) figure 6. f sw(min) frequency clamp 503 504 505 506 507 508 509 510 ? 40 ? 25 ? 105 203550658095110125 f sw(max) (khz) temperature ( c) figure 7. f sw(max) frequency clamp 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 ? 40 ? 25 ? 105 203550658095110125 figure 8. pulldown resistor (r fb ) temperature ( c) r fb (k ) 0.655 0.656 0.657 0.658 0.659 0.660 0.661 ? 40 ? 25 ? 105 20355065809511012 5 v ref(skip) (v) temperature ( c) figure 9. skip/disable threshold (v ref(skip) ) 59.75 59.8 59.85 59.9 59.95 60 60.05 ? 40 ? 20 0 20 40 60 80 100 120
ncp1397a, ncp1397b http://onsemi.com 9 typical characteristics figure 10. source resistance (roh) 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 roha ( ) temperature ( c) 104 105 106 107 108 109 110 111 112 113 114 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) t dead(min) (ns) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) rola ( ) figure 11. sink resistance (rol) figure 12. t dead(min) 286 287 288 289 290 291 292 293 294 295 296 297 ? 40 ? 25 ? 105 203550658095110125 temperature ( c) t dead(nom) (ns) figure 13. t dead(nom) 2.035 2.040 2.045 2.050 2.055 2.060 2.065 ? 40 ? 25 ? 105 203550658095110125 t dead(max) ( s) temperature ( c) figure 14. t dead(max) 4.005 4.010 4.015 4.020 4.025 4.030 4.035 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) v latch (v) figure 15. latch level (v latch )
ncp1397a, ncp1397b http://onsemi.com 10 typical characteristics 1.022 1.024 1.026 1.028 1.030 1.032 1.034 1.036 1.038 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 vbo (v) temperature ( c) figure 16. brown ? out reference (vbo) 27.0 27.2 27.4 27.6 27.8 28.0 28.2 28.4 28.6 28.8 ? 40 ? 25 ? 105 20355065809511012 5 temperature ( c) ibo ( a) figure 17. brown ? out hysteresis current (ibo) 1.032 1.034 1.036 1.038 1.040 1.042 1.044 1.046 1.048 1.050 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v ref(fault) (v) temperature ( c) figure 18. fault input reference (v ref(fault) ) 166 168 170 172 174 176 178 ? 40 ? 25 ? 105 20355065809511012 temperature ( c) i timer1 ( a) figure 19. c timer 1 st current (i timer1 ) 1.530 1.535 1.540 1.545 1.550 1.555 1.560 1.565 ? 40 ? 25 ? 105 203550658095110125 v ref(ocp) (v) temperature ( c) figure 20. ocp reference (v ref ( ocp ) ) 1.25 1.26 1.27 1.28 1.29 1.30 1.31 1.32 1.33 1.34 ? 40 ? 25 ? 105 20355065809511012 temperature ( c) i timer2 (ma) figure 21. c timer 2 nd current (i timer2 )
ncp1397a, ncp1397b http://onsemi.com 11 typical characteristics 4.005 4.010 4.015 4.020 4.025 4.030 4.035 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) v timer(on) (v) figure 22. fault timer ending voltage (v timer(on) ) 0.274 0.276 0.278 0.280 0.282 0.284 0.286 0.288 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 temperature ( c) figure 23. fb fault detection threshold (v fb(fault) ) v fb(off) (v) 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 24. fault timer reset voltage (vt imer(off) ) temperature ( c) v timer(off) (v)
ncp1397a, ncp1397b http://onsemi.com 12 application information the ncp1397a/b includes all necessary features to help building a rugged and safe switch ? mode power supply featuring an extremely low standby power. the below bullets detail the benefits brought by implementing the ncp1397a/b controller: ? wide frequency range : a high ? speed voltage control oscillator allows an output frequency excursion from 50 khz up to 500 khz on m lower and m upper outputs. ? adjustable dead ? time : due to a single resistor wired to ground, the user has the ability to include some dead ? time, helping to fight cross ? conduction between the upper and the lower transistor. ? adjustable soft ? start : every time the controller starts to operate (power on), the switching frequency is pushed to the programmed starting value by external components (r fmin //r fstart ) and slowly moves down toward the minimum frequency, until the feedback loop closes. the soft ? start discharge input (ss(dis)) discharges the soft ? start capacitor before any ic restart excluding the restart after disable is released and fb voltage is higher than 0.3 v. the soft ? start discharge switch also activates in case the fault input detects the overload conditions. ? adjustable minimum and maximum frequency excursion : in resonant applications, it is important to stay away from the resonating peak to keep operating the converter in the right region. thanks to a single external resistor, the designer can program its lowest frequency point, obtained in lack of feedback voltage (during the startup sequence or in short ? circuit conditions). internally trimmed capacitors offer a 3% precision on the selection of the minimum switching frequency. the adjustable upper stop being less precise to 12%. ? low startup current : when directly powered from the high ? voltage dc rail, the device only requires 300 a to startup. ? brown ? out detection : to avoid operation from a low input voltage, it is interesting to prevent the controller from switching if the high ? voltage rail is not within the right boundaries. also, when teamed with a pfc front ? end circuitry, the brown ? out detection can ensure a clean startup sequence with soft ? start, ensuring that the pfc is stabilized before energizing the resonant tank. the bo input features a 28 a hysteresis current for the lowest consumption. ? adjustable fault timer duration : when a fault is detected on the fault input or when the fb path is broken, timer pin starts to charge an external capacitor. if the fault is removed, the timer opens the charging path and nothing happens. when the timer reaches its selected duration (via a capacitor on pin 3), all pulses are stopped. the controller now waits for the discharge via an external resistor on pin 3 to issue a new clean startup sequence via soft ? start. ? cumulative fault events : in the ncp1397a/b, the timer capacitor is not reset when the fault disappears. it actually integrates the information and cumulates the occurrences. a resistor placed in parallel with the capacitor will offer a simple way to adjust the discharge rate and thus the auto ? recovery retry rate. ? overcurrent detection using fault input : the fault input is specifically designed to protect llc application in case of short circuit or overload. in case the voltage on this input grows above first threshold the i timer current source is activated and fault timer capacitor starts charging. simultaneously the soft ? start discharge switch is activated to increase operating frequency of the converter. the ic stops operation in case the fault timer elapses. the fault input includes also second fault comparator that: ? speeds up the fault timer capacitor charging by increasing the i timer1 current to i timer2 ? ncp1397a ? latches off the device ? ncp1397b the second fault comparator thus helps to protect the power stage in case of hard short circuit (like shorted transformer winding etc.) ? skip cycle possibility : the absence of the soft ? start on the skip/disable input (in case the v fb > 0.3 v) offers an easy way to implement skip cycle when power saving features are necessary. a simple resistive divider from the feedback pin to the skip/disable input, and skip can be implemented. ? broken feedback loop detection : upon startup or any time during operation, if the fb signal is missing, the timer starts to charge timer capacitor. if the loop is really broken, the fb level does not grow ? up before the timer ends charging. the controller then stops all pulses and waits until the timer pin voltage collapses to 1 v typically before a new attempt to restart, via the soft ? start. if the optocoupler is permanently broken, a hiccup takes place. ? common collector or common emitter optocoupler connection options : this ic allows the designer to select from two possible optocoupler configurations. voltage ? controlled oscillator the vco section features a high ? speed circuitry allowing operation from 100 khz up to 1 mhz. however, as a division by two internally creates the two q and /q outputs, the final effective signal on output m lower and m upper switches between 50 khz and 500 khz. the vco is configured in such a way that if the feedback pin voltage goes up, the switching frequency also goes up. figure 25 shows the architecture of the vco oscillator.
ncp1397a, ncp1397b http://onsemi.com 13 figure 25. the simplified vco architecture vref v dd rt sets fmin for v(fb) = 0 cint imin + - 0 to ifmax idt fbinternal max f sw max + - + clk d s q q r ab vref v dd rdt sets the deadtime dt imin v dd fmax fmax sets the maximum f sw v cc fb rfb 20 k + - + vfb < vfb(off) start fault timer vb(off) rt the designer needs to program the maximum switching frequency and the minimum switching frequency. in llc configurations, for circuits working above the resonant frequency, a high precision is required on the minimum frequency, hence the 3% specification. this minimum switching frequency is actually reached when no feedback closes the loop. it can happen during the startup sequence, a strong output transient loading or in a short ? circuit condition. by installing a resistor from pin 4 to gnd, the minimum frequency is set. using the same philosophy, wiring a resistor from pin 2 to gnd will set the maximum frequency excursion. to improve the circuit protection features, we have purposely created a dead zone, where the feedback loop has no action. this is typically below 1.1 v. figure 26 details the arrangement where the internal voltage (that drives the vco) varies between 0 and 2.3 v. however, to create this swing, the feedback pin (to which the optocoupler emitter connects), will need to swing typically between 1.1 v and 5.3 v. figure 26. the opamp arrangement limits the vco modulation signal between 0.5 and 2.3 v v cc fb r1 11.3 k ? + + vref 0.5 v r2 8.7 k r3 100 k d1 2.3 v rfmax fmax
ncp1397a, ncp1397b http://onsemi.com 14 this techniques allows us to detect a fault on the converter in case the fb pin cannot rise above 0.3 v (to actually close the loop) in less than a duration imposed by the programmable timer. please refer to the fault section for detailed operation of this mode. as shown on figure 26, the internal dynamics of the vco control voltage will be constrained between 0.5 v and 2.3 v, whereas the feedback loop will drive pin 6 (fb) between 1.1 v and 5.3 v. if we take the default fb pin excursion numbers, 1.1 v = 50 khz, 5.3 v = 500 khz, then the vco maximum slope will be: 500k 50k 4.2 107 khz/v figures 27 and 28 portray the frequency evolution depending on the feedback pin voltage level in a different frequency clamp combination. figure 27. maximal default excursion, rt = 41 k on pin 4 and r f ( max ) = 1.9 k on pin 2 figure 28. here a different minimum frequency was programmed as well as a maximum frequency excursion please note that the previous small ? signal vco slope has now been reduced to 300k / 4.1 = 71 khz / v on m upper and m lower outputs. this offers a mean to magnify the feedback excursion on systems where the load range does not generate a wide switching frequency excursion. due to this option, we will see how it becomes possible to observe the feedback level and implement skip cycle at light loads. it is important to note that the frequency evolution does not have a real linear relationship with the feedback voltage. this is due to the deadtime presence which stays constant as the switching period changes. the selection of the three setting resistors (f max , f min and deadtime) requires the usage of the selection charts displayed below: 50 150 250 350 450 550 1.9 11.9 21.9 31.9 41.9 figure 29. maximum switching frequency resistor selection depending on the adopted minimum switching frequency r fmax (k ) f max (khz) v cc = 15 v v fb = 6.5 v dt = 300 ns f min = 200 khz f min = 50 khz
ncp1397a, ncp1397b http://onsemi.com 15 100 150 200 250 300 350 400 450 500 2468101214161820 r fmin (k ) f min (khz) 20 30 40 50 60 70 80 90 100 20 30 40 50 60 70 80 90 100 110 figure 30. minimum switching frequency resistor selection (f min = 100 khz to 500 khz) figure 31. minimum switching frequency resistor selection (f min = 20 khz to 100 khz) r fmin (k ) f min (khz) v cc = 15 v v fb = 1 v dt = 300 ns v cc = 15 v v fb = 1 v dt = 300 ns 100 300 500 700 900 1100 1300 1500 1700 1900 3.5 13.5 23.5 33.5 43.5 53.5 63.5 73.5 83.5 r dt (k ) dt (ns) figure 32. deadtime resistor selection oring capability and optocoupler connection configurations if for any particular reason, there is a need for a frequency variation linked to an event appearance (instead of abruptly stopping pulses), then the fb pin lends itself very well to the addition of other sweeping loops. several diodes can easily be used perform the job in case of reaction to a fault event or to regulate on the output current (cc operation). figure 33 shows how to do it. figure 33. thanks to the fb configuration, loop oring is easy to implement v cc fb in1 in2 20 k vco the vco configuration used in this ic also offers an easy way to connect optocoupler (or pulldown bipolar) directly to the rt pin instead of fb pin (refer to figures 34 and 35). the optocoupler is then configured as ?common emitter? and the operating frequency is controlled by the current that is taken out from the rt pin ? we have current controller oscillator (cco). if one uses this configuration it is needed to maintain fb pin voltage between 0.3 v and 1 v otherwise the fb fault will be detected. the fb pin can be still used for open fb loop detection in some applications ? to do so it is needed to keep optcoupler emitter voltage higher then 0.3 v for nominal load conditions. one needs to take r fb pulldown resistor into account when using this configuration. it is possible to implement skip mode using skip/disable input and emitter resistors r skip1 and r skip2 .
ncp1397a, ncp1397b http://onsemi.com 16 figure 34. feedback configuration using direct connection to the rt pin ss fmax rt fb skip/disable vcc gnd ncp1397 rskip2 rskip1 rc ok1 rfstart rfmin css fstart(adj) ? rfstart/rfmin fmin(adj) ? rfmin fmax(adj) ? rc + rskip1 + rskip2 figure 35. feedback configuration using direct connection to the rt pin ? no open fb loop detection ss fmax rt fb skip/disable vcc gnd ncp1397 rskip2 rskip1 rc ok1 rfstart rfmin css fstart(adj) ? rfstart/rfmin fmin(adj) ? rfmin fmax(adj) ? rc + rskip1 + rskip2 1n4148 rbias dead ? time control deadtime control is an absolute necessity when the half ? bridge configuration comes to play. the deadtime technique consists in inserting a period during which both high and low side switches are off. of course, the deadtime amount dif fers depending on the switching frequency , hence the ability to adjust it on this controller. the option ranges between 100 ns and 2 s. the deadtime is actually made by controlling the oscillator discharge current. figure 36 portrays a simplified vco circuit based on figure 25. during the discharge time, the clock comparator is high and invalidates the and gates: both outputs are low. when the comparator goes back to the low level, during the timing capacitor ct recharge time, a and b outputs are validated. by connecting a resistor r dt to ground, it creates a current whose image serves to discharge the ct capacitor: we control the dead ? time. the typical range evolves between 100 ns (r dt = 3.5 k ) and 2 s (r dt = 83.5 k ). figure 39 shows the typical waveforms.
ncp1397a, ncp1397b http://onsemi.com 17 figure 36. dead ? time generation v dd i charge : f sw(min) + f sw(max) i dis ct rdt dt vref + 3 v ? 1 v ? + clk d s q q r ab soft ? start sequence in resonant controllers, a soft ? start is needed to avoid suddenly applying the full current into the resonating circuit. with this controller the soft ? start duration is fully adjustable using eternal components. the purpose of the soft ? start pin is to discharge soft ? start capacitor before ic restart and in case of fault conditions detected by fault input. once the controller starts operation, the soft ? start capacitor (refer to figure 37) is fully discharged and thus it starts charging from the rt pin. the charging current increases operating frequency of the controller above f min . as the soft ? start capacitor charges, the frequency smoothly decreases down to f min . of course, practically, the feedback loop is supposed to take over the vco lead as soon as the output voltage has reached the target. if not, then the minimum switching frequency is reached and a fault is detected on the feedback pin (typically below 300 mv). figure 38 depicts a typical llc startup using ncp1397a/b controller. figure 37. soft ? start components arrangement ss fmax rt gnd ncp1397 rf(start) rfmin rfmax css fstart(adj) ? rfstart/rfmin fmin(adj) ? rfmin fmax(adj) ? rfmax figure 38. a typical startup sequence on a llc converter using ncp1397 ss action target is reached please note that the soft ? start capacitor is discharged in the following conditions: ? a startup sequence ? during auto ? recovery burst mode ? a brown ? out recovery ? a temperature shutdown recovery the skip/disable input undergoes a special treatment. since we want to implement skip cycle using this input, we cannot activate the soft ? start every time the feedback pin stops the operations in low power mode. therefore, when the skip/enable pin is released, no soft ? start occurs to offer the best skip cycle behavior. however, it is very possible to combine skip cycle and true disable, e.g. via oring diodes driving pin 8. in that case, if a signal maintains the skip/disable input high long enough to bring the feedback level down (below 0.3 v) since the output voltage starts to fall down, then the soft ? start discharge switch is activated.
ncp1397a, ncp1397b http://onsemi.com 18 0 1.00 2.00 3.00 4.00 0 4.00 8.00 12.0 16.0 time in seconds ? 8.00 ? 4.00 0 4.00 8.00 figure 39. typical oscillator waveforms ct voltage 56.2 65.9 75.7 85.4 95.1 plot3 difference in volts plot2 clock in volts plot1 vct in volts clock pulses dt dt dt a ? b brown ? out protection the brown ? out circuitry (bo) offers a way to protect the resonant converter from low dc input voltages. below a given level, the controller blocks the output pulses, above it, it authorizes them. the internal circuitry, depicted by figure 40, offers a way to observe the high ? voltage (hv) rail. a resistive divider made of r upper and r lower , brings a portion of the hv rail on pin 5. below the turn ? on level, the 28 a current source ibo is off. therefore, the turn ? on level solely depends on the division ratio brought by the resistive divider. figure 40. the internal brown ? out configuration with an offset current source v dd + vbo ? + on/off ibo bo vbulk rupper rlower bo
ncp1397a, ncp1397b http://onsemi.com 19 time in seconds 0 4.0 8.0 12.0 16.0 50 150 250 350 450 figure 41. simulation results for 350 / 250 on / off levels 20 60 100 140 180 vin 250 v 351 v bo plot1 vin in volts vcmp in volts to the contrary, when the internal bo signal is high (m lower and m upper pulse), the ibo source is activated and creates a hysteresis. as a result, it becomes possible to select the turn ? on and turn ? off levels via a few lines of algebra: ibo is off v( ) v bulk1 r lower r lower r upper (eq. 1) ibo is on v( ) v bulk2 r lower r lower r upper (eq. 2) ibo r lower r upper r lower r upper we can now extract r lower from equation 1 and plug it into equation 2, then solve for rupper: r upper r lower v bulk1 vbo vbo r lowerer vbo v bulk1 v bulk2 ibo v bulk1 vbo if we decide to turn ? on our converter for vbulk1 equals 350 v and turn it off for v bulk2 equals 250 v, then we obtain: r upper = 3.57 m r lower = 10.64 k the bridge power dissipation is 400 2 / 3.781 m = 45 mw when front ? end pfc stage delivers 400 v. figure 41 simulation result confirms our calculations. latchoff protection there are some situations where the converter shall be fully turned ? off and stay latched. this can happen in presence of an overvoltage (the feedback loop is drifting) or when an over temperature is detected. thanks to the addition of a comparator on the bo pin, a simple external circuit can lift up this pin above v latch (4 v typical) and permanently disable pulses. the v cc needs to be cycled down below 6.5 v typically to reset the controller.
ncp1397a, ncp1397b http://onsemi.com 20 figure 42. adding a comparator on the bo pin offers a way to latch ? off the controller ? + 20 s rc to permanent latch + v latch v dd ? + bo + vbo bo rlower rupper vbulk v cc q1 ntc vout ibo on figure 42, q1 is blocked and does not bother the bo measurement as long as the ntc and the optocoupler are not activated. as soon as the secondary optocoupler senses an ovp condition, or the ntc reacts to a high ambient temperature, q1 base is brought to ground and the bo pin goes up, permanently latching off the controller. protection circuitry this resonant controller offers a dedicated input (fault input) to detect primary overcurrent conditions and protect power stage from damage. once the voltage on the fault input exceeds 1.04 v threshold the external timer capacitor starts charging by i timer1 current. simultaneously the soft ? start discharge switch is activated to shift operating frequency up to keep primary current at acceptable level. in case the overload disappears fast enough the soft ? start discharge switch is open, i timer1 current turned ? off and timer capacitor discharges via an external parallel resistor. in case the overload lasts for more than timer duration (given by i timer , v timer , c timer and r timer ) the ic stops the operation and waits until the c timer will discharge to 1 v. the application then restarts via soft ? start. in case of heavy overload, like transformer short circuit, the primary current grows very fast and thus could reach danger level prior the fault timer elapses. the ncp1397b therefore features additional comparator (1.55 v) on the fault input to permanently latch the application and protect against destruction. figure 44 depicts the architecture of the fault circuitry for ncp1397b controller. the ncp1397a features second fault comparator as well but in this case it doesn?t latches off the ic but speeds up the fault timer capacitor charging by turning on additional current source i timer2 ? refer to figure 43. the ncp1397a can thus be used in applications that have to recover automatically from any fault conditions.
ncp1397a, ncp1397b http://onsemi.com 21 figure 43. fault input logic for ncp1397a vdd itimer1 reset uvlo rtimer ctimer ctimer + - + vref(fault) + - + vtimeron vtimeroff 1 = ok 0 = fault + - vref(skip) skip/disable + 1 = ok 0 = fault driving logic ss a a b b reset fault average input current to primary fb skip vcc fb ss(dis) css discharge at vcc(on)/ restart if vfb < 0.3 v + - + vref(ocp) vdd itimer2 current sensing circuitry
ncp1397a, ncp1397b http://onsemi.com 22 figure 44. fault input logic for ncp1397b vdd itimer1 reset uvlo rtimer ctimer ctimer + - + vref(fault) + - + vtimeron vtimeroff 1 = ok 0 = fault + - vref(skip) skip/disable + 1 = ok 0 = fault driving logic ss a a b b reset fault average input current to primary fb skip vcc fb ss(dis) css discharge at vcc(on)/ restart if vfb < 0.3 v + - + vref(ocp) current sensing circuitry to latch on figures 43 and 44 examples, a voltage proportional to primary current, once averaged, gives an image of the input power in case v in is kept constant via a pfc circuit. if the output loading increases above a certain level, the voltage on this pin will pass the 1 v threshold and start the timer. if the overload stays there, after a few tens of milli ? seconds, switching pulses will disappear and a protective auto ? recovery cycle will take place. adjusting the resistor r in parallel with the timer capacitor will give the flexibility to adjust the fault burst mode (refer to figure 45).
ncp1397a, ncp1397b http://onsemi.com 23 figure 45. a resistor can easily program the capacitor discharge time 4 v 1 v smps re ? starts smps stops reset at re ? start fault is gone skip/disable fb v cc figure 46. skip cycle can be implemented via two resistors on the fb pin to the fast fault input skip/disable the skip/disable input is not affected by a delayed action. as soon as its voltage exceeds 0.66 v typical, all pulses are off and maintained off as long as the fault is present. when the pin is released, pulses come back and the soft ? start is activated (in case the v fb < 0.3 v). thanks to the low activation level, this pin can observe the feedback pin via a resistive divided and thus implement skip cycle operation. the resonant converter can be designed to lose regulation in light load conditions, forcing the fb level to increase. when it reaches the programmed level, it triggers the skip input and stops pulses. then v out slowly drops, the loop reacts by decreasing the feedback level which, in turn, unlocks the pulses, v out goes up again and so on: we are in skip cycle mode. as the feedback voltage does not drop below 0.3 v the soft ? start discharge switch is not activated in this case. please refer also to figure 35 for skip mode function implementation when optocoupler is connected directly to rt pin. startup behavior when the v cc voltage increases, the internal current consumption is kept below i strup . when v cc reaches the v cc(on) level, output mlower goes high first and then output mupper. this sequence will always be the same whatever triggers the pulse delivery: fault, off to on etc pulsing the output m lower high first gives an immediate charge of the bootstrap capacitor. then, the rest of pulses follow, delivered at the highest switching value, set by the r fstart resistor in parallel with r fmin resistor on pin 4. the soft ? start capacitor ensures a smooth frequency decrease to either the programmed minimum value (in case of fault) or to a value corresponding to the operating point if the feedback loop closes first. figure 47 shows typical signals evolution at power on.
ncp1397a, ncp1397b http://onsemi.com 24 figure 47. at power on, output a is first activated and the frequency slowly decreases based on the soft ? start capacitor voltage figure 47 depicts an auto ? recovery situation, where the timer has triggered the end of output pulses. in that case, the v cc level was given by an auxiliary power supply, hence its stability during the hiccup. a similar situation can arise if the user selects a more traditional startup method, with an auxiliary winding. in that case, the v cc(min) comparator stops the output pulses whenever it is activated, that is to say, when v cc falls below 9.5 v typical. at this time, the v cc pin still receives its bias current from the startup resistor and increases toward v cc(on) . when the voltage reaches v cc(on) , a standard sequence takes place, involving a soft ? start. figure 48 portrays this behavior.
ncp1397a, ncp1397b http://onsemi.com 25 figure 48. when the v cc is to low, all pulses are stopped until v cc goes back to the startup voltage the high ? voltage driver the driver features a traditional bootstrap circuitry, requiring an external high ? voltage diode for the capacitor refueling path. figure 49 shows the internal architecture of the high ? voltage section. figure 49. the internal high ? voltage section of the ncp1397 + vboot mupper hb cboot dboot aux v cc gnd v cc mlower hv uvlo s q q r delay level shifter pulse trigger fault a b
ncp1397a, ncp1397b http://onsemi.com 26 the device incorporates an upper uvlo circuitry that makes sure enough v gs is available for the upper side mosfet. the b and a outputs are delivered by the internal logic, as figure 43 testifies. a delay is inserted in the lower rail to ensure good matching between these propagating signals. as stated in the maximum rating section, the floating portion can go up to 600 vdc and makes the ic perfectly suitable for offline applications featuring a 400 v pfc front ? end stage. ordering information device package shipping ? ncp1397adr2g soic ? 16, less pin 13 (pb ? free) 2500 / tape & reel NCP1397BDR2G soic ? 16, less pin 13 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp1397a, ncp1397b http://onsemi.com 27 package dimensions soic ? 16 nb, less pin 13 case 751am ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. 18 16 9 seating plane l m h x 45 e 15x h e d m 0.25 b m a1 a dim min max millimeters d 9.80 10.00 e 3.80 4.00 a 1.35 1.75 b 0.35 0.49 l 0.40 1.25 e 1.27 bsc c 0.19 0.25 a1 0.10 0.25 m 0 7 h 5.80 6.20 h 0.25 0.50 6.40 15x 0.58 15x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 m 0.25 a s b 15x t b s a b c c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1397/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCP1397BDR2G

	To Download NCP1397BDR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .